An implementation form of mounting chips each having different performance on one package is proposed for the purpose of enhancing density and performance of a semiconductor package. In this case, a high-density inter-chip connection technique excellent in terms of costs is important (see, for example, Patent Literature 1).
Non Patent Literature 1 and Non Patent Literature 2 describe a mode of Package on Package (PoP) connecting different packages by laminating on a package a different package through flip-chip assembly. This PoP is a mode widely adopted in smart phones, tablet terminals, and the like.
Further, as another form for performing high-density implementation of a plurality of chips, there are proposed a packaging technique using an organic substrate having high-density wires (organic interposer), a fan out type packaging technique (FO-WLP: Fan Out-Wafer Level Package) having a through mold via (TMV), a packaging technique using a silicon or glass interposer, a packaging technique using a through silicon via (TSV), a packaging technique using a chip embedded in a substrate for transmission between chips, and the like.
Especially, in the case where semiconductor chips are mounted in the organic interposer and the FO-WLP, a fine wiring layer for allowing the semiconductor chips to have electrical continuity of high density becomes necessary (see, for example, Patent Literature 2).